At the Hot Chips 2023 conference, the Yankee Intel tycoon gave a fresh shot in the "Chip War", presenting the Central Processing Unit (PU) PIUMA (Programmable Integrated Unified Memory Architecture), part of the HIVE (Hierarchical Identify Verify Exploit) of the U.S. Department of defence Advanced investigation Projects Agency (DARPA) Agency, focused on improving results in the analysis of charts on a petabyte scale.
In each of the six PIUMA cores, there are six-six threads, which allows processing data at 1 terabyte per second. The chip consumes only 75W of energy, with only 59% of it per silicone optical connection used, 21% per core. A 7nm goal size processor in FinFET (fin field-effect transistor) was utilized by Taiwan's TSMC (Taiwan Semiconductor Manufacturing Company Limited) with standard Ball Grid Array (BGA) interface.
Data is transmitted utilizing silicon photonic chipsets, for which Ayar Labs is responsible. The 4 chipsets convert electrical signals passing through the microprocessor to optical signals carried by 32 unimodal fibers. Each fibre transmits data at a rate of 32 GB/s, giving a maximum bandwidth of 1 TB/s. The photonic connectors hanging from the sides of the chip let connections to another chips. The Hyper X external optical network provides all-to-all connections for each processing core. It is possible to combine up to 2 million cores with a hold of little than 400 nanoseconds.
Compared to the Intel utilized since the 1970s. Instruction Set Architecture (ISA) architecture x86, PIUMA uses a computer architecture with a reduced instruction set (RISC) that does not encounter specified scaling problems as x86 and, better suited to parallel survival, is more energy-efficient and achieves 8 times better performance in one-thread mode in tasks defined by DARPA.
The position of optical mesh-to-mesh interconnectors propels investigation conducted by NVIDIA, Intel and Ayar Labs, aiming to accomplish solutions that could be implemented on a large scale. Potents see in optical interconnectors a fresh data transfer technique, offering greater bandwidth, lower delays and lower energy consumption compared to conventional chip-to-chip data transfer techniques.
Ronald Lasecki
